This invention relates generally to image sensors. More specifically, the present invention relates to a complementary metal oxide semiconductor (CMOS) image sensor with a dummy pixel or dummy pixel array to enhance image data accuracy.
CMOS imager sensors are becoming more competitive to charge coupled device (CCD) imagers in terms of low cost and easy fabrication with current CMOS processes. These image sensors may be used as the input device in a wide variety of camera systems. One advantage of CMOS image sensors (or imagers) is that signal processing circuits can be readily integrated on the same chip as the imager, thus enabling the design of smart, single-chip camera systems. CMOS imagers are contemplated for use with computers and communication devices to realize low cost videoconferencing. Other applications include robotics, machine vision and automotive electronics. CMOS imager cells (or pixels) store light information as a photocharge on a photodiode or photogate, and then an electrical signal corresponding to the photocharge is read out through a bit line, typically a column data line. Unlike DRAM cells carrying digital data, the imager cell should carry a high resolution analog signal for subsequent conversion to a digital code as high as an 8-bit or 10-bit code with today""s technology. The bit lines have a large capacitance as compared to that of the storage device in the cell. Consequently, the storage cells are usually active cells, which means that the output signal of the cells are amplified or buffered to the bit-line in order to be unaffected by the bit-line capacitance. However, non-linearities in the amplification or buffering leads to errors in the image data.
FIG. 1 schematically illustrates one example of prior art active-pixel CMOS imager circuitry. Imager 10 is an image sensor as disclosed in an article by Mendis et al., entitled xe2x80x9cA 128xc3x97128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systemsxe2x80x9d, IEEE Electron Devices Meeting, p. 583, 1993. A MOS photogate 6 is employed as the light sensitive element in each pixel (imager cell) 18. The transistors within each pixel 18 are typically NMOSFETS. The overall imager 10 is considered a CMOS imager since CMOS electronics are used in conjunction with the imager cells. For example, the transistors 3 within readout circuit 31 are typically PMOSFETS. Imager cells 18 are arranged in rows and columns to form an array, with typically only one row being activated for image data readout at any time. Within each cell 18 photo-charge xe2x80x9cqxe2x80x9d collected under photogate transistor 6 is transferred through a dc-biased transfer gate transistor 8 to a floating diffusion diode 7 formed beneath substrate surface 9. This floating diode 7 is periodically dc-restored by the application of a logic high RESET pulse on the RES bus to the gate of reset FET 11, thus resetting the potential of diode 7 (i.e., at circuit node 17) to the power supply voltage (VDD). Following each diode reset cycle, the photo-charge is transferred to floating diode 7. The voltage on diode 7 then corresponds to the intensity of light incident upon the associated imager cell 18. This voltage sets the potential of the gate of source follower FET 13, which amplifies or buffers the voltage appearing at its gate terminal for subsequent readout. When row select transistor 12 is turned ON by a VROW pulse on row select line RSL, the voltage at circuit node 17 is detected by readout circuit 31 detecting corresponding voltage on column bus 15.
To remove reset noise of reset switch 11, a correlated double sampling (CDS) operation is performed. This involves subtracting the reset level measured on column bus 15 from the signal level on the column bus, where the reset level is obtained just prior to the transfer of photo-charge to diode 7. As such, any offset errors due to transistor mismatches are canceled since both levels are measured at the same circuit point. In the embodiment of Mendis et al., the reset level and the signal level are stored on two separate sample and hold capacitors CR and CS, via two separate switches S1 and S2, respectively. Two identical readout circuit portions are required, one for the reset level, and one for the signal level. Further differential amplification at the multiplexed column output is required to complete the reset noise removal operation.
As mentioned above, the source follower FET 13 amplifies or buffers the voltage level on circuit node 17 such that the image data will be unperturbed by the column data bus capacitance. A problem with this approach is that the source follower is non-ideal, such that the transfer characteristic between the pixel voltage at node 17 and the output voltage on column bus 15 is non-linear. This non-linearity stems from the relationship between threshold voltage and gate voltage. If the source follower is an NMOS fabricated by conventional CMOS processes, the backgate is typically not tied to the source, resulting in a threshold voltage that changes with input (gate) voltage. The larger the source voltage is relative to the substrate voltage, the larger is the threshold voltage, leading to the nonlinear characteristic. Thus, a higher gate voltage produces a higher threshold voltage, resulting in an output signal that is attenuated relative to the ideal case. A similar nonlinearity occurs if the source follower is a PMOS. In either case, the nonlinear transfer characteristic produces a conversion error from the light source to the output image data.
Electronic shuttering capability can be incorporated within CMOS image sensors by the addition of a shutter transistor within each pixel. When this shutter transistor is pulsed on, the photocharge stored by the photosensitive element is transferred to a storage node within the pixel. The storage charge is then read out sequentially row by row. A problem with this approach, however, is that leakage current at the storage node can severely degrade the signal integrity thereat. As the number of pixels grows to realize high resolution pictures, the time required to scan all the pixels also grows. Hence, the total amount of charge lost by leakage becomes significant, thereby degrading the overall picture quality. In addition, since the charge is read sequentially row by row, the lost charge in the pixels are all different according to their row order. One common solution to this problem is to reduce the leakage current; however, leakage current reduction is difficult to implement. It usually involves expensive manufacturing equipment to minimize leakage current at the p-n junction (source or drain to substrate) of the shutter transistor.
Accordingly, there is a need to overcome the deficiencies of image quality degradation due to threshold voltage variation in CMOS image sensors, and due to leakage current in image sensors with electronic shuttering.
The present invention relates to an image sensor including one or more dummy pixels that produce a reference signal which is used to compensate for errors within the devices of the main pixel cells. In a first embodiment, at least one dummy pixel is used in conjunction with other circuitry to correct for nonlinearities in the transfer characteristic of a source follower transistor within each pixel. The dummy pixel may be used in conjunction with A/D converters connected directly to column data lines of the main pixel array. A plurality of comparators and up/down counters may be used to perform directed correlated double sampling with threshold voltage compensation. In a second embodiment, an array of dummy pixels is used to correct for leakage current within the pixels which is present during an electronic shutter mode of operation. The dummy pixel array may be used in conjunction with a dummy pixel compensating for threshold voltage variation, whereby errors due to both leakage current and threshold voltage mismatch are corrected.